hasankursun/soc-builder-rtl-v1
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AbiralArch/hardware-cvdp-examples
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AbiralArch/hardware-verilogeval-v2
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AbiralArch/hardware-shailja-vgen
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AbiralArch/hardware-cvdp-complete
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xxrjun/rtllm-variants
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architect-ubc-capstone/rtl-augmented
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architect-ubc-capstone/rtl-augmented-v2
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architect-ubc-capstone/rtl-augmented-v3
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VN-26/rtl-llm-dataset
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Adel9st/Verilog-Turkish-Dataset
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billshockley/titanbench
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vyomaalabs/verixa-dataset
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KSU-HW-SEC/SynthAgentic-Eval
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Rajasrl/VLSI-Dataset
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EvanOLeary/rtllm-shinka-evolve
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Elinnos/elinnos-sv-v7-training-data
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rishr/fairchild-rtl-coder-sft-mixture
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