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| <title id="title">PAX Coder commercial architecture</title> | |
| <desc id="desc">Commercial architecture diagram for GGUF Q4_K_M tensors, PAX GEMM ABI, CPU reference validation, CUDA device gate, and MoE expert execution.</desc> | |
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| <text class="title" x="56" y="64">PAX Coder Commercial Runtime Surface</text> | |
| <text class="small" x="58" y="96">Proprietary SNAPKITTYWEST product path: GGUF weights -> verified interfaces -> staged deployment gates</text> | |
| <rect class="panel" x="56" y="140" width="240" height="144" rx="8"/> | |
| <text class="label" x="80" y="178">GGUF Input</text> | |
| <text class="small" x="80" y="214">Q4_K_M tensors</text> | |
| <text class="tiny" x="80" y="244">router, gate, up, down</text> | |
| <text class="tiny" x="80" y="266">commercial weights only</text> | |
| <rect class="panel2" x="376" y="140" width="248" height="144" rx="8"/> | |
| <text class="label" x="400" y="178">PAX GEMM ABI</text> | |
| <text class="small" x="400" y="214">shape, dtype, layout</text> | |
| <text class="tiny" x="400" y="244">C boundary is the contract</text> | |
| <text class="tiny" x="400" y="266">PTX handle is explicit</text> | |
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| <text class="label" x="728" y="150">CPU Reference</text> | |
| <text class="small" x="728" y="184">edge suite PASS</text> | |
| <text class="tiny" x="728" y="212">staging-ready path</text> | |
| <rect class="blocked" x="704" y="264" width="244" height="132" rx="8"/> | |
| <text class="label" x="728" y="302">CUDA Device Gate</text> | |
| <text class="small" x="728" y="336">requires nvcc + ptxas</text> | |
| <text class="tiny" x="728" y="364">compile and device run</text> | |
| <text class="tiny" x="728" y="386">before GPU production</text> | |
| <rect class="gate" x="1028" y="176" width="202" height="160" rx="8"/> | |
| <text class="label" x="1052" y="214">MoE Execution</text> | |
| <text class="small" x="1052" y="250">router logits</text> | |
| <text class="small" x="1052" y="278">SwiGLU gate/up</text> | |
| <text class="small" x="1052" y="306">down projection</text> | |
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| <text class="label" x="82" y="508">Commercial Control</text> | |
| <text class="tiny" x="82" y="540">No implied license. No redistribution.</text> | |
| <text class="tiny" x="82" y="566">Commercial use requires written authorization.</text> | |
| <text class="tiny" x="82" y="592">Weights, PTX, docs, and kernels are covered.</text> | |
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| <text class="label" x="482" y="508">Evidence Boundary</text> | |
| <text class="tiny" x="482" y="540">CPU tests are runtime evidence.</text> | |
| <text class="tiny" x="482" y="566">PTX text is handle evidence.</text> | |
| <text class="tiny" x="482" y="592">Lean/GPU status requires current tool runs.</text> | |
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| <text class="label" x="882" y="508">Deployment Rule</text> | |
| <text class="tiny" x="882" y="540">CPU path can stage after edge tests pass.</text> | |
| <text class="tiny" x="882" y="566">GPU production waits for device harness PASS.</text> | |
| <text class="tiny" x="882" y="592">Manifest must match loaded tensor names.</text> | |
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